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sq1912aeeh www.vishay.com vishay siliconix s15-1251 rev. a, 01-jun-15 1 document number: 62983 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 automotive dual n-channel 20 v (d-s) 175 c mosfet marking code : 8r features ? trenchfet ? power mosfet ? aec-q101 qualified ? 100 % r g tested ? typical esd protection: 800 v ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 notes a. package limited. b. pulse test; pulse width 300 s, duty cycle 2 %. c. when mounted on 1" square pcb (fr4 material). product summary v ds (v) 20 r ds(on) ( ) at v gs = 4.5 v 0.280 r ds(on) ( ) at v gs = 2.5 v 0.360 r ds(on) ( ) at v gs = 1.8 v 0.450 i d (a) 0.8 configuration dual s ot-363 s c-70 dual (6 lea d s) top view 1 s 1 2 g 1 3 d 2 d 1 6 g 2 5 s 2 4 d 1 s 1 g 1 3 k d 2 s 2 g 2 3 k ordering information package sc-70 lead (pb)-free and halogen-free sq1912aeeh-t1-ge3 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 20 v gate-source voltage v gs 12 continuous drain current a t c = 25 c i d 0.8 a t c = 125 c 0.8 continuous source curre nt (diode conduction) a i s 0.8 pulsed drain current b i dm 3 maximum power dissipation b t c = 25 c p d 1.5 w t c = 125 c 0.5 operating junction and storage temperature range t j , t stg -55 to +175 c thermal resistance ratings parameter symbol limit unit junction-to-ambient pcb mount c r thja 220 c/w junction-to-foot (drain) r thjf 100
sq1912aeeh www.vishay.com vishay siliconix s15-1251 rev. a, 01-jun-15 2 document number: 62983 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not subj ect to production testing. c. independent of operating temperature. d. gate is obscured by esd network series resistance and cannot be tested directly. stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. specifications (t c = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0, i d = 250 a 20 - - v gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.45 0.6 1.5 gate-source leakage i gss v ds = 0 v, v gs = 4.5 v - - 1 a v ds = 0 v, v gs = 12 v - - 10 ma zero gate voltage drain current i dss v gs = 0 v v ds = 20 v - - 1 a v gs = 0 v v ds = 20 v, t j = 125 c - - 50 v gs = 0 v v ds = 20 v, t j = 175 c - - 150 on-state drain current a i d(on) v gs = 4.5 v v ds 5 v 1.5 - - a drain-source on-state resistance a r ds(on) v gs = 4.5 v i d = 1.2 a - 0.200 0.280 v gs = 4.5 v i d = 1.2 a, t j = 125 c - - 0.423 v gs = 4.5 v i d = 1.2 a, t j = 175c - - 0.510 v gs = 2.5 v i d = 1 a - 0.261 0.360 v gs = 1.8 v i d = 0.2 a - 0.320 0.450 forward transconductance b g fs v ds = 10 v, i d = 1.2 a - 2.6 - s dynamic b input capacitance c iss v gs = 0 v v ds = 10 v, f = 1 mhz -27- pf output capacitance c oss -19- reverse transfer capacitance c rss -7- total gate charge c q g v gs = 4.5 v v ds = 10 v, i d = 1.2 a - 1 1.25 nc gate-source charge c q gs -0.14- gate-drain charge c q gd -0.27- gate resistance d r g f = 1 mhz 1.5 3 4.5 k turn-on delay time c t d(on) v dd = 10 v, r l = 20 i d ? 0.5 a, v gen = 4.5 v, r g = 1 -6682 ns rise time c t r - 108 135 turn-off delay time c t d(off) - 715 893 fall time c t f - 390 487 source-drain diode ratings and characteristics b pulsed current a i sm --3a forward voltage v sd i f = 0.5 a, v gs = 0 - 0.8 1.2 v
sq1912aeeh www.vishay.com vishay siliconix s15-1251 rev. a, 01-jun-15 3 document number: 62983 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) gate current vs. gate-source voltage output characteristics transconductance gate current vs. gate-source voltage transfer characteristics on-resistance vs. drain current 0.000 0.001 0.002 0.003 0.004 0.005 0 5 10 15 20 25 i gss - g ate current (ma) v gs - g ate-to- s ource voltage (v) t j = 25 c 0.0 0.4 0.8 1.2 1.6 2.0 0.0 0.2 0.4 0.6 0.8 1.0 i d - drain current (a) v d s -drain-to- s ource voltage (v) v gs = 5 v thru 2 v v gs = 1 v v gs = 1.5 v 0 1 2 3 4 5 0.0 0.2 0.4 0.6 0.8 1.0 g f s -tran s conductance ( s ) i d - drain current (a) t c = 125 c t c = - 55 c t c = 25 c 10 0 10 -2 10 -4 10 -6 10 -8 10 -10 0 4 8 12 16 20 i gss - g ate current (a) v gs - g ate-to- s ource voltage(v) t j = 150 c t j = 25 c 0.0 0.4 0.8 1.2 1.6 2.0 0.0 0.5 1.0 1.5 2.0 2.5 i d - drain current (a) v gs - g ate-to- s ource voltage (v) t c = - 55 c t c = 125 c t c = 25 c 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.4 0.8 1.2 1.6 2.0 r d s (on) -on-re s i s tance () i d - drain current (a) v gs = 4.5 v v gs = 2.5 v v gs = 1.8 v
sq1912aeeh www.vishay.com vishay siliconix s15-1251 rev. a, 01-jun-15 4 document number: 62983 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) capacitance on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage gate charge source drain diode forward voltage threshold voltage 0 20 40 60 80 0 5 10 15 20 c - capacitance (pf) v d s -drain-to- s ource voltage (v) c i ss c o ss c r ss 0.5 0.8 1.1 1.4 1.7 2.0 - 50 - 25 0 25 50 75 100 125 150 175 r d s (on) -on-re s i s tance (normalized) t j - junction temperature ( c) i d = 1.2 a v gs = 4.5 v v gs = 2.5 v 0.0 0.2 0.4 0.6 0.8 1.0 012345 r d s (on) -on-re s i s tance () v gs - g ate-to- s ource voltage (v) t j = 150 c t j = 25 c 0 1 2 3 4 5 0.0 0.2 0.4 0.6 0.8 1.0 v gs - g ate-to- s ource voltage (v) q g -total g ate charge (nc) i d = 1.2 a 0.001 0.01 0.1 1 10 0.00.20.40.60.81.01.2 i s - s ource current (a) v s d - s ource-to-drain voltage (v) t j = 25 c t j = 150 c - 0.5 - 0.3 - 0.1 0.1 0.3 0.5 - 50 - 25 0 25 50 75 100 125 150 175 v gs (th) variance (v) t j - temperature ( c) i d = 250 a i d = 5 ma
sq1912aeeh www.vishay.com vishay siliconix s15-1251 rev. a, 01-jun-15 5 document number: 62983 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) drain source breakdown vs . junction temperature safe operating area 20 22 24 26 28 30 - 50 - 25 0 25 50 75 100 125 150 175 v d s -drain-to- s ource voltage (v) t j - junction temperature ( c) i d = 1 ma 0.01 0.1 1 10 100 0.01 0.1 1 10 100 i d - drain current (a) v d s -drain-to- s ource voltage (v) * v gs > minimum v gs at which r d s (on) i s s pecified 100 m s limited by r d s (on) * i dm limited t c = 25 c s ingle pul s e bvd ss limited 10 m s 1 s , 10 s , dc
sq1912aeeh www.vishay.com vishay siliconix s15-1251 rev. a, 01-jun-15 6 document number: 62983 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 thermal ratings (t a = 25 c, unless otherwise noted) normalized thermal transient impedance, junction-to-ambient normalized thermal transient impedance, junction-to-foot note ? the characteristics shown in the two graphs - normalized transient thermal impedance junction-to-ambient (25 c) - normalized transient thermal impedance junction-to-foot (25 c) are given for general guidelines only to enable the user to ge t a ball park indication of part capabilities. the data are ext racted from single pulse transient thermal impedance characteristics which are developed from empirical measurements. the latter is valid for the part mounted on printed circuit board - fr4, size 1" x 1" x 0.062" , double sided with 2 oz. copper, 100 % on both sides. the part ca pabilities can widely vary depending on actual application parameters and operating conditions. vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62983 . 10 -3 10 -2 0 0 6 0 1 1 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 s ingle pul s e duty cycle = 0.5 sq uare wave pul s e duration ( s ) normalized effective tran s ient thermal impedance 1. duty cycle, d = 2. per unit ba s e = r thja = 220 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 note s : 4. s urface mounted p dm 0.02 10 -3 10 -2 0 1 1 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized effective transient thermal impedance 0.02
ordering information www.vishay.com vishay siliconix revision: 06-oct-15 1 document number: 65839 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 sc-70 ordering codes for the sq rugged series power mosfets in the sc-70 package: note a. old ordering code is obsolete and no longer valid for new orders datasheet part number o ld ordering code a new ordering code sq1421eeh sq1421eeh-t1-ge3 sq1421eeh-t1_ge3 sq1431eh sq1431eh-t1-ge3 sq1431eh-t1_ge3 sq1440eh - sq1440eh-t1_ge3 sq1470aeh - sq1470aeh-t1_ge3 sq1539eh - sq1539eh-t1_ge3 sq1563aeh - sq1563aeh-t1_ge3 sq1902ael - sq1902ael-t1_ge3 sq1912aeeh - sq1912aeeh-t1_ge3
l c e e 1 e d e 1 a 2 a a 1 1 -a- b -b- 23 654 package information vishay siliconix document number: 71154 06-jul-01 www.vishay.com 1

dim min nom max min nom max a 0.90 ? 1.10 0.035 ? 0.043 a 1 ? ? 0.10 ? ? 0.004 a 2 0.80 ? 1.00 0.031 ? 0.039 b 0.15 ? 0.30 0.006 ? 0.012 c 0.10 ? 0.25 0.004 ? 0.010 d 1.80 2.00 2.20 0.071 0.079 0.087 e 1.80 2.10 2.40 0.071 0.083 0.094 e 1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65bsc 0.026bsc e 1 1.20 1.30 1.40 0.047 0.051 0.055 l 0.10 0.20 0.30 0.004 0.008 0.012 7 nom 7 nom ecn: s-03946?rev. b, 09-jul-01 dwg: 5550
an816 vishay siliconix document number: 71405 12-dec-03 www.vishay.com 1 dual-channel little foot 6-pin sc-70 mosfet copper leadframe version recommended pad pattern and thermal performance introduction the new dual 6-pin sc-70 package with a copper leadframe enables improved on-resistance values and enhanced thermal performance as compared to the existing 3-pin and 6-pin packages with alloy 42 leadframes. these devices are intended for small to medium load applications where a miniaturized package is required. devices in this package come in a range of on-resistance values, in n-channel and p-channel versions. this technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for the dual-channel version. pin-out figure 1 shows the pin-out description and pin 1 identification for the dual-channel sc-70 device in the 6-pin configuration. both n-and p-channel devices are available in this package ? the drawing example below illustrates the p-channel device. figure 1. sot-363 sc-70 (6-leads) 6 4 1 2 3 5 top view s 1 g 1 d 2 d 1 g 2 s 2 for package dimensions see outline drawing sc-70 (6-leads) ( http://www.vishay.com/doc?71154 ) basic pad patterns see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ) for the sc-70 6-pin basic pad layout and dimensions. this pad pattern is sufficient for the low-power applications for which this package is intended. increasing the drain pad pattern (figure 2) yields a reduction in thermal resistance and is a preferred footprint. figure 2. sc-70 (6 leads) dual 48 (mil) 16 (mil) 654 3 2 1 61 (mil) 26 (mil) 8 (mil) 0.0 (mil) 23 (mil) 71 (mil) 96 (mil) 26 (mil) 87 (mil) evaluation board for the dual- channel sc70-6 the 6-pin sc-70 evaluation board (evb) shown in figure 3 measures 0.6 in. by 0.5 in. the copper pad traces are the same as described in the previous section, basic pad patterns . the board allows for examination from the outer pins to the 6-pin dip connections, permitting test sockets to be used in evaluation testing. the thermal performance of the dual 6-pin sc-70 has been measured on the evb, comparing both the copper and alloy 42 leadframes. this test was then repeated using the 1-inch 2 pcb with dual-side copper coating. a helpful way of displaying the thermal performance of the 6-pin sc-70 dual copper leadframe is to compare it to the traditional alloy 42 version.
an816 vishay siliconix www.vishay.com 2 document number: 71405 12-dec-03 figure 3. front of board sc70-6 back of board sc70-6 d1 g2 s2 s1 g1 d2 sc70 ? 6 dual vishay.com thermal performance junction-to-foot thermal resistance (the package performance) thermal performance for the dual sc-70 6-pin package is measured as junction-to-foot thermal resistance, in which the ?foot? is the drain lead of the device as it connects with the body. the junction-to -foot thermal resistance for this device is typically 80 c/w, with a maximum thermal resistance of approximately 100 c/w. this data compares favorably with another compact, dual-channel package ? the dual tsop-6 ? which features a typical thermal resistance of 75 c/w and a maximum of 90 c/w. power dissipation the typical r ja for the dual-channel 6-pin sc-70 with a copper leadframe is 224 c/w steady-state, compared to 413 c/w for the alloy 42 version. all figures are based on the 1-inch 2 fr4 test board. the following example shows how the thermal resistance impacts power dissipation for the dual 6-pin sc-70 package at varying ambient temperatures. alloy 42 leadframe alloy 42 leadframe room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 413 o c w p d 303 mw p d t j(max) t a r ja p d 150 o c 60 o c 413 o c w p d 218 mw cooper leadframe room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 224 o c w p d 558 mw p d t j(max) t a r ja p d 150 o c 60 o c 224 o c w p d 402 mw although they are intended for low-power applications, devices in the 6-pin sc-70 dual-channel configuration will handle power dissipation in excess of 0.5 w. testing to further aid the comparison of copper and alloy 42 leadframes, figures 4 and 5 illustrate the dual-channel 6-pin sc-70 thermal performance on two different board sizes and pad patterns. the measured steady-state values of r ja for the dual 6-pin sc-70 with varying leadframes are as follows: little foot 6-pin sc-70 alloy 42 copper 1) minimum recommended pad pattern on the evb board (see figure 3). 518 c/w 344 c/w 2) industry standard 1-inch 2 pcb with maximum copper both sides. 413 c/w 224 c/w the results indicate that designers can reduce thermal resistance ( ja) by 34% simply by using the copper leadframe device as opposed to the alloy 42 version. in this example, a 174 c/w reduction was achieved without an increase in board area. if an increase in board size is feasible, a further 120 c/w reduction can be obtained by utilizing a 1-inch 2 . pcb area. the dual copper leadframe versions have the following suf fix: dual: si19xxedh compl.: si15xxedh
an816 vishay siliconix document number: 71405 12-dec-03 www.vishay.com 3 time (secs) figure 4. dual sc70-6 thermal performance on evb thermal resistance (c/w) 0 1 500 100 200 100 1000 300 10 10 -1 10 -2 10 -3 10 -4 10 -5 alloy 42 400 time (secs) figure 5. dual sc70-6 comparison on 1-inch 2 pcb thermal resistance (c/w) 0 1 500 100 200 100 1000 300 10 10 -1 10 -2 10 -3 10 -4 10 -5 400 copper copper alloy 42
application note 826 vishay siliconix www.vishay.com document number: 72602 18 revision: 21-jan-08 application note recommended minimum pads for sc-70: 6-lead 0.096 (2.438) recommended mi nimum pads dimensions in inches/(mm) 0.067 (1.702) 0.026 (0.648) 0.045 (1.143) 0.016 (0.406) 0.026 (0.648) 0.010 (0.241) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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